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ltc3890 1 3890fb typical a pplica t ion fea t ures a pplica t ions descrip t ion 60v low i q , dual, 2-phase synchronous step-down dc/dc controller high efficiency dual 8.5v/3.3v output step-down converter n wide v in range: 4v to 60v (65v abs max) n low operating i q : 50a (one channel on) n wide output voltage range: 0.8v v out 24v n r sense or dcr current sensing n out-of-phase controllers reduce required input capacitance and power supply induced noise n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n selectable continuous, pulse-skipping or low ripple burst mode ? operation at light loads n selectable current limit n very low dropout operation: 99% duty cycle n adjustable output voltage soft-start or t racking n power good output voltage monitors n output overvoltage protection n low shutdown i q : < 14a n internal ldo powers gate drive from v in or extv cc n no current foldback during start-up n small low profile (0.75mm) 5mm 5mm qfn package n automotive always-on systems n battery operated digital devices n distributed dc power systems efficiency and power loss vs output current the ltc ? 3890 is a high performance dual step-down switching regulator dc/dc controller that drives all n-channel synchronous power mosfet stages. a constant frequency current mode architecture allows a phase- lockable frequency of up to 850khz. power loss and noise due to the esr of the input capacitor are minimized by operating the two controller output stages out-of-phase. the 50a no-load quiescent current extends operating run time in battery-powered systems. opti-loop ? compensa - tion allows the transient response to be optimized over a wide range of output capacitance and esr values. the ltc3890 features a precision 0.8v reference and power good output indicators. a wide 4v to 60v input supply range encompasses a wide range of intermediate bus voltages and battery chemistries. independent track/ss pins for each controller ramp the output voltages during start-up. current foldback limits mosfet heat dissipation during short-circuit conditions. the pllin/mode pin selects among burst mode operation, pulse-skipping mode, or continuous conduction mode at light loads. for a leaded package version (28-lead narrow ssop), see the ltc3890-1 data sheet. l , lt, ltc, ltm, burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258, 7230497. output current (a) 0 efficiency (%) power loss (mw) 70 100 10.1 0.01 0.001 0.0001 10 3890 ta01b 50 40 30 20 1 10 100 1000 10000 0.1 10 60 80 90 v in = 12v v out = 3.3v 0.1f 100k 4.7h 1000pf 470f 22f 0.008 31.6k 34.8k v out1 3.3v 5a 330f 0.1f 4.7f 100k 8h 1000pf 0.01 10.5k 34.8k v out2 8.5v 3a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 ith1 ith2 v in intv cc track/ss1 track/ss2 v in 9v to 60v 3890 ta01a 0.1f 0.1f ltc3890
ltc3890 2 3890fb p in c on f igura t ion a bsolu t e maxi m u m r a t ings (note 1) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 top view sense1 ? freq phasmd clkout pllin/mode sgnd run1 run2 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sense1 + v fb1 ith1 track/ss1 i lim pgood1 tg1 sw1 sense2 ? sense2 + v fb2 ith2 track/ss2 pgood2 tg2 sw2 uh package 32-lead (5mm 5mm) plastic qfn 33 sgnd t jmax = 150c, v ja = 34c/w exposed pad (pin 33) is sgnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3890euh#pbf ltc3890euh#trpbf 3890 32-lead (5mm w 5mm) plastic qfn C40c to 125c ltc3890iuh#pbf ltc3890iuh#trpbf 3890 32-lead (5mm w 5mm) plastic qfn C40c to 125c ltc3890huh#pbf ltc3890huh#trpbf 3890 32-lead (5mm w 5mm) plastic qfn C40c to 150c ltc3890mpuh#pbf ltc3890mpuh#trpbf 3890 32-lead (5mm w 5mm) plastic qfn C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ input supply voltage (v in ) ......................... C0 .3v to 65v topside driver voltages boost1, boost2 ................................. C 0.3v to 71v switch voltage (sw1, sw2) ......................... C 5v to 65v (boost1-sw1), (boost2-sw2) ................ C 0.3v to 6v run1, run2 ............................................... C 0.3v to 8v maximum current sourced into pin from source > 8v ..................................................... 10 0a sense1 + , sense2 + , sense1 C sense2 C voltages ..................................... C 0.3v to 28v pllin/mode voltage ................................... C0 .3v to 6v freq voltage ........................................ C0 .3v to intv cc i lim , phasmd voltages ....................... C0 .3v to intv cc extv cc ..................................................... C0 .3v to 14v ith1, ith2, v fb1 , v fb2 voltages ................... C 0.3v to 6v pgood1, pgood2 voltages ....................... C 0.3v to 6v track/ss1, track/ss2 voltages ............. C 0.3v to 6v operating junction temperature range (notes 2, 3) ltc3890e, ltc3890i ......................... C 40c to 125c ltc3890h .......................................... C 40c to 150c ltc3890mp ....................................... C 55c to 150c storage temperature range .................. C 65c to 150c e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in input supply operating voltage range 4 60 v v fb1,2 regulated feedback voltage (note 4) i th1,2 voltage = 1.2v C40c to 85c, all grades ltc3890e, ltc3890i ltc3890h, ltc3890mp l l 0.792 0.788 0.786 0.800 0.800 0.800 0.808 0.812 0.812 v v v the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted. (note 2)
ltc3890 3 3890fb symbol parameter conditions min typ max units i fb1,2 feedback current (note 4) 5 50 na v reflnreg reference voltage line regulation (note 4) v in = 4.5v to 60v 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop, ? ith voltage = 1.2v to 0.7v l 0.01 0.1 % (note 4) measured in servo loop, ? ith voltage = 1.2v to 2v l C0.01 C0.1 % g m1,2 transconductance amplifier g m (note 4) i th1,2 = 1.2v, sink/source = 5a 2 mmho i q input dc supply current (note 5) pulse-skipping or forced continuous mode (one channel on) run1 = 5v and run2 = 0v, v fb1 = 0.83v or run1 = 0v and run2 = 5v, v fb2 = 0.83v 1.3 ma pulse-skipping or forced continuous mode (both channels on) run1,2 = 5v, v fb1,2 = 0.83v (no load) 2 ma sleep mode (one channel on) run1 = 5v and run2 = 0v, v fb1 = 0.83v (no load) or run1 = 0v and run2 = 5v, v fb2 = 0.83v (no load) 50 75 a sleep mode (both channels on) run1,2 = 5v, v fb1,2 = 0.83v (no load) 60 100 a shutdown run1,2 = 0v 14 25 a uvlo undervoltage lockout intv cc ramping up intv cc ramping down l l 3.6 3.92 3.80 4.2 4.0 v v feedback overvoltage protection measured at v fb1,2 , relative to regulated v fb1,2 7 10 13 % i sense + sense + pin current each channel 1 a i sense C sense C pins current each channel v sense C < intv cc C 0.5v v sense C > intv cc + 0.5v 700 1 a a maximum tg1, 2 duty factor in dropout 98 99 % i track/ss1,2 soft-start charge current v track/ss1,2 = 0v 0.7 1.0 1.4 a v run1 v run2 run1 pin on threshold run2 pin on threshold v run1 rising v run2 rising l l 1.15 1.20 1.21 1.25 1.27 1.30 v v run1,2 pin hysteresis 50 mv v sense(max) maximum current sense threshold v fb1,2 = 0.7v, v sense1 C, 2 C = 3.3v, i lim = 0 v fb1,2 = 0.7v, v sense1 C, 2 C = 3.3v, i lim = intv cc v fb1,2 = 0.7v, v sense1 C, 2 C = 3.3v, i lim = float l l l 22 43 64 30 50 75 36 57 85 mv mv mv gate driver tg1,2 pull-up on-resistance tg1,2 pull-down on-resistance 2.5 1.5 bg1,2 pull-up on-resistance bg1,2 pull-down on-resistance 2.4 1.1 tg1,2 t r tg1,2 t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 16 ns ns bg1,2 t r bg1,2 t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 28 13 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 30 ns e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted. (note 2)
ltc3890 4 3890fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted. (note 2) symbol parameter conditions min typ max units bg/tg t 1d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 95 ns intv cc linear regulator v intvccvin internal v cc voltage 6v < v in < 60v, v extvcc = 0v 4.85 5.1 5.35 v v ldovin intv cc load regulation i cc = 0ma to 50ma, v extvcc = 0v 0.7 1.1 % v intvccext internal v cc voltage 6v < v extvcc < 13v 4.85 5.1 5.35 v v ldoext intv cc load regulation i cc = 0ma to 50ma, v extvcc = 8.5v 0.6 1.1 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 4.9 v v ldohys extv cc hysteresis 250 mv oscillator and phase-locked loop f 25k programmable frequency r freq = 25k, pllin/mode = dc voltage 105 khz f 65k programmable frequency r freq = 65k, pllin/mode = dc voltage 375 440 505 khz f 105k programmable frequency r freq = 105k, pllin/mode = dc voltage 835 khz f low low fixed frequency v freq = 0v, pllin/mode = dc voltage 320 350 380 khz f high high fixed frequency v freq = intv cc , pllin/mode = dc voltage 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 850 khz pgood1 and pgood2 outputs v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative hysteresis C13 C10 2.5 C7 % % v fb with respect to set regulated voltage v fb ramping positive hysteresis 7 10 2.5 13 % % t pg delay for reporting a fault 25 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum ratings for extended periods may affect device reliability and lifetime. note 2: the ltc3890 is tested under pulsed load conditions such that t j t a . the ltc3890e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the l tc3890i is guaranteed over the C40c to 125c operating junction temperature range, the ltc3890h is guaranteed over the C40c to 150c operating junction temperature range and the ltc3890mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 34c/w) note 4: the ltc3890 is tested in a feedback loop that servos v ith1,2 to a specified voltage and measures the resultant v fb . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the ltc3890e/ltc3890i, 150c for the ltc3890h/ltc3890mp). for the ltc3890mp, the specification at C40c is not tested in production and is assured by design, characterization and correlation to production testing at C55c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section).
ltc3890 5 3890fb typical p er f or m ance c harac t eris t ics efficiency and power loss vs output current efficiency vs output current load step burst mode operation load step forced continuous mode load step pulse-skipping mode inductor current at light load soft start-up tracking start-up efficiency vs input voltage output current (a) figure 13 circuit 0 efficiency (%) power loss (mw) 70 100 10.1 0.01 0.001 0.0001 10 3890 g01 50 40 30 20 1 10 100 1000 10000 0.1 10 60 80 90 v in = 12v v out = 3.3v burst efficiency ccm loss pulse-skipping loss burst loss ccm efficiency pulse-skipping efficiency output current (a) 0 efficiency (%) 70 100 10.1 0.01 0.001 0.0001 10 3890 g02 50 40 30 20 10 60 80 90 v out = 8.5v v out = 3.3v v in = 12v burst mode operation figure 13 circuit input voltage (v) 80 efficiency (%) 94 100 20 30 35 40 45 50 55 60 151050 25 3890 g03 90 88 86 84 82 92 96 98 v out1 = 3.3v v out2 = 8.5v i load = 2a figure 13 circuit v in = 12v v out = 3.3v figure 13 circuit 50s/div 3890 g04 v out 100mv/div ac- coupled i l 2a/div v in = 12v v out = 3.3v figure 13 circuit 50s/div 3890 g05 v out 100mv/div ac- coupled i l 2a/div v in = 12v v out = 3.3v figure 13 circuit 50s/div 3890 g06 v out 100mv/div ac- coupled i l 2a/div v in = 12v v out = 3.3v i load = 200a 5s/div 3890 g07 forced continuous mode pulse-skipping mode burst mode operation 1a/div figure 13 circuit 2ms/div 3890 g08 v out2 2v/div v out1 2v/div figure 13 circuit 2ms/div 3890 g09 v out2 2v/div v out1 2v/div
ltc3890 6 3890fb typical p er f or m ance c harac t eris t ics total input supply current vs input voltage extv cc switchover and intv cc voltages vs temperature intv cc line regulation maximum current sense voltage vs i th voltage sense C pin input bias current maximum current sense threshold vs duty cycle foldback current limit quiescent current vs temperature intv cc vs load current duty cycle (%) 0 maximum current sense voltage (mv) 50 40 60 70 80 3890 g15 30 20 20 40 50 100 80 60 10 30 90 70 i lim = float i lim = intv cc i lim = gnd feedback voltage (mv) 0 maximum current sense voltage (mv) 40 60 800 3890 g16 20 0 200 400 500 80 30 50 10 70 600 100 300 700 i lim = float i lim = intv cc i lim = gnd input voltage (v) 0 supply current (a) 200 300 20 30 35 40 45 50 55 60 65 15105 25 3890 g10 150 100 50 250 no load 300a load v out = 3.3v figure 13 circuit temperature (c) ?75 4.0 extv cc and intv cc voltage (v) 4.2 4.6 4.8 5.0 6.0 5.4 ?25 25 50 75 100 3890 g11 4.4 5.6 5.8 5.2 ?50 0 125 150 intv cc extv cc rising extv cc falling input voltage (v) 3.0 intv cc voltage (v) 4.0 4.5 5.5 20 30 35 40 45 50 55 60 65 15100 5 25 3890 g12 3.5 5.0 i load = 10ma v sense common mode voltage (v) 0 sense ? current (a) 20 3890 g14 400 300 10 15 5 25 800 700 600 500 200 100 0 ?100 temperature (c) ?75 quiescent current (a) 75 50250 3890 g17 60 50 ?50 ?25 75 45 30 40 35 80 70 65 55 100 125 150 v in = 12v load current (ma) 0 intv cc voltage (v) 5.25 40 3890 g18 4.50 20 60 4.00 5.50 5.00 4.75 4.25 80 100 extv cc = 5v extv cc = 8.5v extv cc = 0v v in = 12v v ith (v) 0 current sense theshold (mv) 40 60 80 0.6 1.0 3890 g13 20 0 0.2 0.4 0.8 1.2 1.4 ?20 ?40 burst mode operation pulse-skipping mode 5% duty cycle forced continuous mode i lim = float i lim = intv cc i lim = gnd
ltc3890 7 3890fb typical p er f or m ance c harac t eris t ics track/ss pull-up current vs temperature shutdown (run) threshold vs temperature regulated feedback voltage vs temperature sense C pin total input bias current vs temperature shutdown current vs input voltage oscillator frequency vs temperature undervoltage lockout threshold vs temperature oscillator frequency vs input voltage shutdown current vs temperature input voltage (v) 0 shutdown current (a) 10 15 30 25 20 30 35 40 45 50 55 60 65 15105 25 3890 g23 5 20 input voltage (v) 344 oscillator frequency (khz) 348 350 356 20 30 35 40 45 50 55 60 65 15105 25 3890 g26 346 352 354 freq = gnd temperature (c) ?75 sense ? current (a) 50250 3890 g22 400 300 ?25?50 75 800 700 600 500 200 100 0 ?100 125100 150 v out > intv cc + 0.5v v out < intv cc ? 0.5v temperature (c) ?75 regulated feedback voltage (mv) 806 0 25 50 3890 g21 800 796 ?50 ?25 75 794 792 808 804 802 798 100 125 150 temperature (c) ?75 frequency (khz) 500 550 600 0 25 50 100 3890 g24 450 400 ?50 ?25 75 125 150 350 300 freq = gnd freq = intv cc temperature (c) ?75 intv cc voltage (v) 3.7 3.8 3.9 4.1 ?25 75 100 3890 g25 3.6 4.2 4.0 ?50 0 25 50 125 150 falling rising temperature (c) 8 shutdown current (a) 12 14 22 20 25 50 75 100 125 150 ?25 ?75 ?50 0 3890 g27 10 16 18 v in = 12v temperature (c) ?75 0.90 track/ss current (a) 0.95 1.00 1.05 1.10 ?50 ?25 0 755025 3890 g19 100 125 150 temperature (c) ?75 run pin voltage (v) 1.30 1.35 1.40 0 50 75 3890 g20 1.25 1.20 ?50 ?25 25 100 125 150 1.15 1.00 1.05 1.10 run1 falling run2 rising run1 rising run2 falling
ltc3890 8 3890fb p in func t ions sense1 C , sense2 C (pin 1, pin 9): the (C) input to the differential current comparators. when greater than intv cc C 0.5v, the sense C pin supplies current to the current comparator. freq (pin 2): the frequency control pin for the internal vco. connecting the pin to gnd forces the vco to a fixed low frequency of 350khz. connecting the pin to intv cc forces the vco to a fixed high frequency of 535khz. other frequencies between 50khz and 900khz can be programmed using a resistor between freq and gnd. an internal 20a pull-up current develops the voltage to be used by the vco to control the frequency. phasmd (pin 3): control input to phase selector which determines the phase relationships between control - ler 1, controller 2 and the clkout signal. pulling this pin to ground forces tg2 and clkout to be out of phase 180 and 60 with respect to tg1. connecting this pin to int v cc forces tg2 and clkout to be out of phase 240 and 120 with respect to tg1. floating this pin forces tg2 and clkout to be out of phase 180 and 90 with respect to tg1. refer to table 1. clkout (pin 4): output clock signal available to daisy- chain other controller ics for additional mosfet driver stages/phases. the output levels swing from intv cc to ground. pllin/mode (pin 5): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, the phase-locked loop will force the rising tg1 signal to be synchronized with the rising edge of the external clock. when not syn- chronizing to an external clock, this input, which acts on both controllers, determines how the ltc3890 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2v and less than intv cc C 1.3v selects pulse-skipping operation. sgnd (pins 6, exposed pad pin 33): small-signal ground common to both controllers, must be routed separately from high current grounds to the common (C) terminals of the c in capacitors. the exposed pad must be soldered to pcb ground for rated thermal performance. run1, run2 (pin 7, pin 8): digital run control inputs for each controller. forcing run1 below 1.16v or run2 below 1.20v shuts down that controller. forcing both of these pins below 0.7v shuts down the entire ltc3890, reducing quiescent current to approximately 14a. intv cc (pin 19): output of the internal linear low dropout regulator. the driver and control circuits are powered from this voltage source. must be decoupled to power ground with a minimum of 4.7f ceramic or other low esr ca- pacitor. do not use the intv cc pin for any other purpose. extv cc (pin 20): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power, bypassing the internal ldo powered from v in whenever extv cc is higher than 4.7v. see extv cc connection in the applications information section. do not float or exceed 14v on this pin. pgnd (pin 21): driver power ground. connects to the sources of bottom (synchronous) n-channel mosfets and the (C) terminal(s) of c in . v in (pin 22): main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin. bg1, bg2 (pin 23, pin 18): high current gate drives for bottom (synchronous) n-channel mosfets. voltage swing at these pins is from ground to intv cc . boost1, boost2 (pin 24, pin 17): bootstrapped supplies to the topside floating drivers. capacitors are connected between the boost and sw pins and schottky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). sw1, sw2 (pin 25, pin 16): switch node connections to inductors.
ltc3890 9 3890fb tg1, tg2 (pin 26, pin 15): high current gate drives for top n-channel mosfets. these are the outputs of float - ing drivers with a voltage swing equal to intv cc C 0.5v superimposed on the switch node voltage sw. pgood1, pgood2 (pin 27, pin 14): open-drain logic output. pgood1,2 is pulled to ground when the voltage on the v fb1,2 pin is not within 10% of its set point. i lim (pin 28): current comparator sense voltage range inputs. tying this pin to sgnd, float or intv cc sets the maximum current sense threshold to one of three different levels for both comparators. track/ss1, track/ss2 (pin 29, pin 13): external tracking and soft-start input. the ltc3890 regulates the v fb1,2 voltage to the smaller of 0.8v or the voltage on the track/ss1,2 pin. an internal 1a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to final regulated output voltage. p in func t ions alternatively, a resistor divider on another voltage supply connected to this pin allows the ltc3890 output to track the other supply during start-up. ith1, ith2 (pin 30, pin 12): error amplifier outputs and switching regulator compensation points. each associ- ated channels current comparator trip point increases with this control voltage. v fb1 , v fb2 (pin 31, pin 11): receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. sense1 + , sense2 + (pin 32, pin 10): the (+) input to the differential current comparators are normally connected to dcr sensing networks or current sensing resistors. the ith pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold.
ltc3890 10 3890fb func t ional diagra m sw 25, 16 top boost 24, 17 tg 26, 15 c b c in d b clkout pgnd bot bg 23, 18 intv cc intv cc v in c out v out 3890 fd r sense drop out det bot top on s r q q shdn sleep 0.425v icmp 2.7v 0.65v ir 3mv slope comp duplicate for second controller channel sense + 32, 10 sense ? 1, 9 pgood1 v fb1 0.88v 0.72v l 27 21 + ? + ? + ? + ? pgood2 freq v fb2 0.88v 0.72v + ? + ? + ? + ? 14 + ? + ? switch logic v fb 31, 11 r a c c r c c c2 r b 0.80v track/ss 0.88v 7a (run1) 0.5a (run2) 11v run 7, 8 ith 30, 12 track/ss 29, 13 + ? c ss 1a shdn current limit foldback shdn rst 2(v fb ) 4 phasmd 3 2 pllin/mode 20a vco ldo en intv cc 5.1v sync det 100k clk2 clk1 c lp 5 i lim 28 v in extv cc 20 22 ldo pfd en 4.7v 5.1v + ? 19 sgnd 33 ea ov
ltc3890 11 3890fb o pera t ion (refer to the functional diagram) main control loop the ltc3890 uses a constant frequency, current mode step-down architecture with the two controller channels operating 180 degrees out-of-phase. during normal op - eration, each external top mosfet is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the error amplifier compares the output voltage feedback signal at the v fb pin, (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage. when the load current increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the ith voltage until the average inductor current matches the new load current. after the top mosfet is turned off each cycle, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is tied to a voltage less than 4.7v, the v in ldo (low dropout linear regulator) supplies 5.1v from v in to intv cc . if extv cc is taken above 4.7v, the v in ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies 5.1v from extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as one of the ltc3890 switching regulator outputs. each top mosfet driver is biased from the floating boot- strap capacitor, c b , which normally recharges during each cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one twelfth of the clock period every tenth cycle to allow c b to recharge. shutdown and start-up (run1, run2 and track/ ss1, track/ss2 pins) the two channels of the ltc3890 can be independently shut down using the run1 and run2 pins. pulling either of these pins below 1.15v shuts down the main control loop for that controller. pulling both pins below 0.7v disables both controllers and most internal circuits, including the intv cc ldos. in this state, the ltc3890 draws only 14a of quiescent current. releasing either run pin allows a small internal current to pull up the pin to enable that controller. the run1 pin has a 7a pull-up current while the run2 pin has a smaller 0.5a. the 7a current on run1 is designed to be large enough so that the run1 pin can be safely floated (to always enable the controller) without worry of condensa - tion or other small board leakage pulling the pin down. this is ideal for always-on applications where one or both controllers are enabled continuously and never shut down. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low impedance source, do not exceed the absolute maximum rating of 8v. the run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v in ), so long as the maximum current into the run pin does not exceed 100a. the start-up of each controllers output voltage v out is controlled by the voltage on the track/ss pin for that channel. when the voltage on the track/ss pin is less than the 0.8v internal reference, the ltc3890 regulates the v fb voltage to the track/ss pin voltage instead of the 0.8v reference. this allows the track/ss pin to be used to program a soft-start by connecting an external capacitor from the track/ss pin to sgnd. an internal 1a pull-up current charges this capacitor creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from 0v to 0.8v (and beyond up to 5v), the output voltage v out rises smoothly from zero to its final value. alternatively the track/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the track/ss pin an external resistor divider from the other supply to ground (see the applications information section).
ltc3890 12 3890fb o pera t ion (refer to the functional diagram) light load current operation (burst mode operation, pulse-skipping or forced continuous mode) (pllin/mode pin) the ltc3890 can be enabled to enter high efficiency burst mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. to select burst mode operation, tie the pllin/ mode pin to a dc voltage below 0.8v (e.g., sgnd). to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when a controller is enabled for burst mode operation, the minimum peak current in the inductor is set to approxi- mately 25% of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith voltage drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the ith pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc3890 draws. if one channel is shut down and the other channel is in sleep mode, the ltc3890 draws only 50a of quiescent current. if both channels are in sleep mode, the ltc3890 draws only 60a of quiescent current. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the ith pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse cur - rent comparator, ir, turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation or clocked by an external clock source to use the phase-locked loop (see frequency selection and phase-locked loop section), the induc- tor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous opera - tion has the advantage of lower output voltage ripple and less interference to audio circuitry. in forced continuous mode, the output ripple is independent of load current. when the pllin/mode pin is connected for pulse-skipping mode, the ltc3890 operates in pwm pulse-skipping mode at light loads. in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator, icmp, may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade-off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3890s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to sgnd, tied to intv cc or programmed through an external resistor. tying freq to sgnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and sgnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 10.
ltc3890 13 3890fb o pera t ion (refer to the functional diagram) a phase-locked loop (pll) is available on the ltc3890 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the ltc3890s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of controller 1s external top mosfet to the ris - ing edge of the synchronizing signal. thus, the turn-on of controller 2s external top mosfet is 180 degrees out of phase to the rising edge of the external clock sour ce. the vco input voltage is prebiased to the operating fre- quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of tg1. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the phase-locked loop is from approximately 55khz to 1mhz, with a guarantee to be between 75khz and 850khz. in other words, the ltc3890s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.1v (falling). polyphase applications (clkout and phasmd pins) the ltc3890 features two pins (clkout and phasmd) that allow other controller ics to be daisy-chained with the ltc3890 in polyphase applications. the clock output signal on the clkout pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or multiple separate outputs. the phasmd pin is used to adjust the phase of the clkout signal as well as the relative phases between the two internal controllers, as summarized in table 1. the phases are calculated relative to the zero degrees phase being defined as the rising edge of the top gate driver output of controller 1 (tg1). table 1 v phasmd controller 2 phase clkout phase gnd 180 60 floating 180 90 intv cc 240 120 output overvoltage protection an overvoltage comparator guards against transient over - shoots as well as other more serious conditions that may overvoltage the output. when the v fb pin rises by more than 10% above its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood1 and pgood2) pins each pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the corresponding v fb pin voltage is not within 10% of the 0.8v reference voltage. the pgood pin is also pulled low when the corresponding run pin is low (shut down). when the v fb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. foldback current when the output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, pro - gressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. foldback current limiting is disabled during the soft-start interval (as long as the v fb voltage is keeping up with the track/ss voltage). theory and benefits of 2-phase operation why the need for 2-phase operation? up until the 2 - phase family , constant-frequency dual switching regulators operated both channels in phase (i.e., single phase operation). this means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. these large amplitude current pulses increased the total rms current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and battery.
ltc3890 14 3890fb o pera t ion (refer to the functional diagram) with 2-phase operation, the two channels of the dual switching regulator are operated 180 degrees out-of-phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a significant reduction in total rms input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for emi and improves real world operating efficiency. figure 1 compares the input waveforms for a representa- tive single-phase dual switching regulator to the ltc3890 2-phase dual switching regulator. an actual measurement of the rms input current under these conditions shows that 2-phase operation dropped the input current from 2.53a rms to 1.55a rms . while this is an impressive reduction in itself, remember that the power losses are proportional to i rms 2 , meaning that the actual power wasted is reduced by a fac - tor of 2.66. the reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera- tion is a function of the dual switching regulators relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 2 shows how the rms input current varies for single-phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase op- eration are not just limited to a narrow operating range, for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one chan- nel operating at maximum current and 50% duty cycle. i in(meas) = 2.53a rms i in(meas) = 1.55a rms 3890 f01 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div figure 1. input waveforms comparing single-phase (a) and 2-phase (b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves efficiency figure 2. rms input current comparison input voltage (v) 0 input rms current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3890 f02 single phase dual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a
ltc3890 15 3890fb a pplica t ions i n f or m a t ion the typical application on the first page is a basic ltc3890 application circuit. ltc3890 can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets and schottky diodes are selected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maxi- mum current limit of the controller. when i lim is grounded, the maximum current limit threshold voltage of the cur - rent comparator is programmed to be 30mv. when i lim is floated, the maximum current limit threshold is 75mv. when i lim is tied to intv cc , the maximum current limit threshold is set to 50mv. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. the common mode voltage range on these pins is 0v to 28v (abs max), enabling the ltc3890 to regulate output voltages up to a nominal 24v (allowing margin for tolerances and transients). the sense + pin is high impedance over the full common mode range, drawing at most 1a. this high impedance allows the current comparators to be used in inductor dcr sensing. the impedance of the sense C pin changes depending on the common mode voltage. when sense C is less than intv cc C 0.5v, a small current of less than 1a flows out of the pin. when sense C is above intv cc + 0.5v, a higher current (~700a) flows into the pin. between intv cc C 0.5v and intv cc + 0.5v, the current transitions from the smaller current to the higher current. filter components mutual to the sense lines should be placed close to the ltc3890, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 3). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if inductor dcr sensing is used (figure 4b), sense resistor r1 should be c out to sense filter, next to the controller inductor or r sense 3890 f03 figure 3. sense lines placement with inductor or sense resistor (4a) using a resistor to sense current (4b) using the inductor dcr to sense current figure 4. current sensing methods v in v in r sense intv cc boost tg sw bg place capacitor near sense pins sense + r1* c1* *r1 and c1 are optional. sense ? sgnd ltc3890 v out 3890 f04a v in v in intv cc boost tg sw bg *place c1 near sense pins inductor dcrl sense + sense ? sgnd ltc3890 v out 3890 f04b r1 r2c1* (r1 || r2) ? c1 = l dcr r sense(eq) = dcr r2 r1 + r2
ltc3890 16 3890fb a pplica t ions i n f or m a t ion placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 4a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the current comparator threshold voltage sets the peak of the induc - tor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (30mv, 50mv or 75mv, depending on the state of the i lim pin). when using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability cri- terion for buck regulators operating at greater than 50% duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak inductor current depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3890 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 4b. the dcr of the inductor represents the small amount of dc resistance of the copper wire, which can be less than 1m for today s low value, high current inductors. in a high current application requiring such an inductor, power loss through a sense resistor would cost several points of efficiency compared to inductor dcr sensing. if the external (r1||r2) ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (30mv, 50mv or 75mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. when provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coefficient of copper resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value (r d ), use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current.
ltc3890 17 3890fb a pplica t ions i n f or m a t ion the equivalent resistance r1|| r2 is scaled to the room temperature inductance and maximum dcr: r1|| r2 = l dcr at 20c ( ) ? c1 the sense resistor values are: r1 = r1|| r2 r d ; r2 = r1 ? r d 1C r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) C v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet switching and gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current, ? i l , decreases with higher induc- tance or higher frequency and increases with higher v in : ? i l = 1 f ( ) l ( ) v out 1C v out v in ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.3(i max ). the maximum ?i l occurs at the maximum input voltage. the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher ?i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection two external power mosfets must be selected for each controller in the ltc3890: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch.
ltc3890 18 3890fb a pplica t ions i n f or m a t ion the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5.1v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. pay close attention to the bv dss specification for the mosfets as well. selection criteria for the power mosfets include the on-resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc C v thmin + 1 v thmin ? ? ? ? ? ? f ( ) p sync = v in C v out v in i max ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diodes d3 and d4 shown in figure 11 conduct during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead-time and requiring a reverse recover y period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection the selection of c in is simplified by the 2-phase architec - ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula shown in equation 1 to determine the maximum
ltc3890 19 3890fb a pplica t ions i n f or m a t ion rms capacitor current requirement. increasing the out- put current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/ 2 (1) this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3890, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the ltc3890 2-phase operation can be cal - culated by using equation 1 for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2 - phase system. the overall benefit of a multiphase design will only be fully realized when the sour ce impedance of the power supply/battery is included in the efficiency testing. the drains of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3890, is also suggested. a 10 resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: ? v out ? i l esr + 1 8 ? f ? c out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and ?i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. setting output voltage the ltc3890 output voltages are each set by an external feedback resistor divider carefully placed across the out- put, as shown in figure 5. the regulated output voltage is determined by: v out = 0.8v 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feedforward ca - pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. 1/2 ltc3890 v fb v out r b c ff r a 3890 f05 figure 5. setting output voltage
ltc3890 20 3890fb a pplica t ions i n f or m a t ion tracking and soft-start (track/ss pins) the start-up of each v out is controlled by the voltage on the respective track/ss pin. when the voltage on the track/ss pin is less than the internal 0.8v reference, the ltc3890 regulates the v fb pin voltage to the voltage on the track/ss pin instead of 0.8v. the track/ss pin can be used to program an external soft-start function or to allow v out to track another supply during start-up. soft-start is enabled by simply connecting a capacitor from the track/ss pin to ground, as shown in figure 6. an internal 1a current sour ce charges the capacitor, providing a linear ramping voltage at the track/ss pin. the ltc3890 will regulate the v fb pin (and hence v out ) according to the voltage on the track/ss pin, allowing v out to rise smoothly from 0v to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 0.8v 1a time v x(master) v out(slave) output voltage 3890 f07a time 3890 f07b v x(master) v out(slave) output voltage 1/2 ltc3890 v out v x v fb track/ss 3890 f08 r b r a r tracka r trackb (7a) coincident tracking (7b) ratiometric tracking figure 8. using the track/ss pin for tracking 1/2 ltc3890 track/ss c ss sgnd 3890 f06 figure 6. using the track/ss pin to program soft-start alternatively, the track/ss pin can be used to track two (or more) supplies during start-up, as shown qualitatively in figures 7a and 7b. to do this, a resistor divider should be connected from the master supply (v x ) to the track/ ss pin of the slave supply (v out ), as shown in figure 8. during start-up v out will track v x according to the ratio set by the resistor divider: v x v out = r a r tracka ? r tracka + r trackb r a + r b for coincident tracking (v out = v x during start-up): r a = r tracka r b = r trackb figure 7. two different modes of output voltage tracking
ltc3890 21 3890fb a pplica t ions i n f or m a t ion intv cc regulators the ltc3890 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the intv cc pin from either the v in supply pin or the extv cc pin depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the ltc3890s internal circuitry. the v in ldo and the extv cc ldo regulate intv cc to 5.1v. each of these can supply a peak current of 50ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor. no matter what type of bulk capacitor is used, an additional 1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3890 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the v in ldo or the extv cc ldo. when the voltage on the extv cc pin is less than 4.7v, the v in ldo is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency consid - erations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the ltc3890 intv cc current is limited to less than 32ma from a 40v supply when not using the extv cc supply at a 70c ambient temperature: t j = 70c + (32ma)(40v)(43c/w) = 125c to prevent the maximum junction temperature from be - ing exceeded, the input supply current must be checked while operating in forced continuous mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the v in ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.5v. the extv cc ldo attempts to regulate the intv cc voltage to 5.1v, so while extv cc is less than 5.1v, the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 5.1v, up to an absolute maximum of 14v, intv cc is regulated to 5.1v. using the extv cc ldo allows the mosfet driver and control power to be derived from one of the ltc3890s switching regulator outputs (4.7v v out 14v) during normal operation and from the v in ldo when the output is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc ldo than is speci- fied, an external schottky diode can be added between the extv cc and intv cc pins. in this case, do not apply more than 6v to the extv cc pin and make sure that extv cc v in . significant efficiency and thermal gains can be realized by powering intv cc from the output, since the v in cur - rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). for 5v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to an 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (32ma)(8.5v)(43c/w) = 82c however, for 3.3v and other low voltage outputs, additional circuitry is required to derive intv cc power from the output.
ltc3890 22 3890fb extv cc v in tg1 sw bg1 pgnd 1/2 ltc3890 r sense v out nds7002 c out 3890 f09 mbot mtop c in l bat85 bat85 bat85 figure 9. capacitive charge pump for extv cc the following list summarizes the four possible connec- tions for extv cc : 1. e xtv cc grounded. this will cause intv cc to be powered from the internal 5.1v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. ext v cc connected directly to v out . this is the normal connection for a 5v to 14v regulator and provides the highest efficiency. 3. ext v cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc < v in . 4. ext v cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with the capacitive charge pump shown in figure 9. ensure that extv cc < v in . a pplica t ions i n f or m a t ion desired mosfet. this enhances the top mosfet switch and turns it on. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . the external diode d b can be a schottky diode or silicon diode, but in either case it should have low-leakage and fast recovery. pay close attention to the reverse leakage current specification for this diode, especially at high temperatures where it generally increases substantially. for applications with output voltages greater than ~5v that are switching infrequently, a leaky diode d b can fully discharge the bootstrap capacitor c b , creating a current path from the output voltage to the boost pin to intv cc . not only does this increase the quiescent current of the converter, but it can cause intv cc to rise to dangerous levels if the leakage exceeds the current consumption on intv cc . particularly, this is a concern in burst mode operation at no load or very light loads, where the part is switching very infrequently and the current draw on intv cc is very low (typically about 35a). generally, pulse-skipping and forced continuous modes are less sensitive to leakage, since the more frequent switching keeps the bootstrap capacitor c b charged, preventing a current path from the output voltage to intv cc . however, in cases where the converter has been operat - ing (in any mode) and then is shut down, if the leakage of diode d b fully discharges the bootstrap capacitor c b before the output voltage discharges to below ~5v, then the leakage current path can be created from the output voltage to intv cc . in shutdown, the intv cc pin is able to sink about 30a. to accommodate diode leakage greater than this amount in shutdown, intv cc can be loaded with an external resistor or clamped with a zener diode. alternatively, the pgood resistor can be used to sink the current (assuming the resistor pulls up to intv cc ) since pgood is pulled low when the converter is shut down. nonetheless, using a low-leakage diode is the best choice to maintain low quiescent current under all conditions. topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the
ltc3890 23 3890fb a pplica t ions i n f or m a t ion fault conditions: current limit and current foldback the ltc3890 includes current foldback to help limit load current when the output is shorted to ground. if the output voltage falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 45% of its maximum selected value. under short-circuit conditions with very low duty cycles, the ltc3890 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time, t on(min) , of the ltc3890 (95ns), the input voltage and inductor value: ? i l(sc) = t on(min) v in l ? ? ? ? ? ? the resulting average short-circuit current is: i sc = 45% ? i lim(max) C 1 2 ? i l(sc) fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the control- ler is operating. a comparator monitors the output for overvoltage condi - tions. the comparator detects faults greater than 10% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. phase-locked loop and frequency synchronization the ltc3890 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (vco). this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the turn-on of controller 2s top mosfet is thus 180 degrees out of phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced continu - ously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, c lp , holds the voltage at the vco input. figure 10. relationship between oscillator frequency and resistor value at the freq pin freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3890 f10 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125
ltc3890 24 3890fb a pplica t ions i n f or m a t ion note that the ltc3890 can only be synchronized to an external clock whose frequency is within range of the ltc3890s internal vco, which is nominally 55khz to 1mhz. this is guaranteed to be between 75khz and 850khz. typically, the external clock (on the pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.1v. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchro- nization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchro- nization. although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. table 2 summarizes the different states in which the freq pin can be used. table 2 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor dc voltage 50khz to 900khz any of the above external clock phase locked to external clock minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3890 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in f ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3890 is approximately 95ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.
ltc3890 25 3890fb a pplica t ions i n f or m a t ion efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power . although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3890 circuits: 1) ic v in current, 2) in- tv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc from an output-derived source power through extv cc will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/ (efficiency). for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis - tor and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resis- tances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (t y pically 15v or greater). transition losses can be estimated from: transition loss = (1.7) ? v in ? 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is ver y important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. the ltc3890 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including body diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss.
ltc3890 26 3890fb a pplica t ions i n f or m a t ion checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recov- ery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti - loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in figure 13 circuit will provide an adequate starting point for most applications. the ith series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca- pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de- creasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma.
ltc3890 27 3890fb a pplica t ions i n f or m a t ion design example as a design example for one channel, assume v in = 12v (nominal), v in = 22v (max), v out = 3.3v, i max = 5a, v sense(max) = 75mv and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the freq pin to gnd, generating 350khz operation. the minimum inductance for 30% ripple current is: ? i l = v out f ( ) l ( ) 1C v out v in(nom) ? ? ? ? ? ? ? ? a 4.7h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.73a. increasing the ripple current will also help ensure that the minimum on-time of 95ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) f ( ) = 3.3v 22v 350khz ( ) = 429ns the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (64mv): r sense 64mv 5.73a 0.01 ? choosing 1% resistors: r a = 25k and r b = 78.7k yields an output voltage of 3.32v. the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v 5a ( ) 2 1+ 0.005 ( ) 50 c C 25 c ( ) ? ? ? ? 0.035 ? ( ) + 22v ( ) 2 5a 2 2.5 ? ( ) 215pf ( ) ? 1 5v C 2.3v + 1 2.3v ? ? ? ? ? ? 350khz ( ) = 331mw a short-circuit to ground will result in a folded back cur - rent of: i sc = 34mv 0.01 ? C 1 2 95ns 22v ( ) 4.7h ? ? ? ? ? ? = 3.18a with a typical value of r ds(on) and = (0.005/c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = 3.28a ( ) 2 1.125 ( ) 0.022 ? ( ) = 250mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.02(1.45a) = 29mv p-p
ltc3890 28 3890fb a pplica t ions i n f or m a t ion figure 11. recommended printed circuit layout diagram c b2 c b1 c1* c2* r1* r pu1 pgood1 v pull-up c intvcc c in d1* 1f ceramic m1 m2 m3 m4 d2* c vin v in r in l1 l2 c out1 v out1 gnd v out2 3890 f11 c out2 r sense r sense r pu2 pgood2 v pull-up f in 1f ceramic ith1 v fb1 sense1 + sense1 ? freq sense2 ? sense2 + v fb2 ith2 track/ss2 track/ss1 pgood2 pgood1 tg1 sw1 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sw2 tg2 ilim phasmd clkout pllin/mode run1 run2 sgnd + + + ltc3890 r2* *r1, r2, c1, c2, d1, d2 are optional.
ltc3890 29 3890fb a pplica t ions i n f or m a t ion r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3890 f12 r sense2 v out2 c out2 figure 12. branch current waveforms
ltc3890 30 3890fb a pplica t ions i n f or m a t ion pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 11. figure 12 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets mtop1 and mtop2 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter - minals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the ltc3890 v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur - rent peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposites channel s voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3890 and occupy minimum pc trace area. 7. use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic.
ltc3890 31 3890fb pc board layout debugging start with one controller on at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switch - ing node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 15% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementa- tion. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompen - sation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual perfor - mance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage. a pplica t ions i n f or m a t ion
ltc3890 32 3890fb efficiency and power loss vs output current efficiency vs load current efficiency vs input voltage typical a pplica t ions figure 13. high efficiency dual 8.5v/3.3v step-down converter mtop2 sense1 + sense1 ? v fb1 track/ss2 ith2 v fb2 sense2 ? sense2 + ith1 track/ss1 i lim phsmd clkout pllin/mode sgnd extv cc run1 run2 freq pgood2 bg1 c ith1a 100pf c ith1 1000pf c ss2 0.01f c ss1 0.01f c ith2 470pf c1 1nf c out1 470f r a1 31.6k r ith1 34.8k r b1 100k r b2 100k r freq 41.2k r ith2 34.8k mtop1, mtop2, mbot1, mbot2: rjk0651dpb l1: coilcraft ser1360-472kl l2: coilcraft ser1360-802kl c out1 : sanyo 6tpe470m c out2 : sanyo 10tpe330m d1, d2: dfls1100 d1 d2 ltc3890 r sense1 8m r sense2 10m l1 4.7h l2 8h mbot1 tg1 mtop1 v out1 3.3v 5a v in 9v to 60v 3890 ta02a 100k pgood1 intv cc 100k c b1 0.1f r a2 10.5k sw1 v out2 8.5v 3a sw2 boost1 c b2 0.1f boost2 v in intv cc pgnd tg2 bg2 c out2 330f c int 4.7f c in 220f mbot2 c2 1nf v out2 output current (a) 0 eeficiency (%) power loss (mw) 70 100 10.1 0.01 0.001 0.0001 10 3890 ta02b 50 40 30 20 1 10 100 1000 10000 0.1 10 60 80 90 v in = 12v v out = 3.3v burst efficiency ccm loss pulse-skipping loss burst loss ccm efficiency pulse-skipping efficiency output current (a) 0 eeficiency (%) 70 100 10.1 0.01 0.001 0.0001 10 3890 ta02c 50 40 30 20 10 60 80 90 v out = 8.5v v out = 3.3v v in = 12v input voltage (v) 80 eeficiency (%) 94 100 20 30 35 40 45 50 55 60 151050 25 3890 ta02d 90 88 86 84 82 92 96 98 v out1 = 3.3v v out2 = 8.5v i load = 2a
ltc3890 33 3890fb typical a pplica t ions mtop2 sense1 + sense1 ? v fb1 track/ss2 ith2 v fb2 sense2 ? sense2 + ith1 track/ss1 i lim phsmd clkout pllin/mode extv cc run1 run2 freq pgood2 pgood1 bg1 c ith1a 100pf c ith1 470pf c ss1 0.01f c1 1nf c out1 330f r a1 10.5k r ith1 34.8k r b1 100k r run 1000k r mode 100k mtop1, mtop2, mbot1, mbot2: rjk0651dpb l1, l2: coilcraft ser1360-802kl c out1 , c out2 : sanyo 10tpe330m d1, d2: dfls1100 d1 d2 ltc3890 r sense1 10m r sense2 10m l1 8h l2 8h mbot1 tg1 mtop1 v out1 8.5v 6a v in 9v to 60v 3890 ta03 intv cc 100k c b1 0.1f sw1 sw2 boost1 c b2 0.1f boost2 v in intv cc pgnd tg2 bg2 c out2 330f c int 4.7f c in 220f mbot2 c2 1nf c ith2 100pf v out intv cc v in sgnd r freq 41.2k high efficiency 8.5v dual-phase step-down converter
ltc3890 34 3890fb typical a pplica t ions mtop2 sense1 + sense1 ? v fb1 track/ss2 ith2 v fb2 sense2 ? sense2 + ith1 track/ss1 i lim phsmd clkout pllin/mode sgnd extv cc run1 run2 freq pgood2 pgood1 bg1 c ith1a 100pf c ith1 470pf c ss2 0.01f c ss1 0.01f c ith2 470pf c1 1nf c out1 180f r a1 6.98k r ith1 34.8k r b1 100k r b2 100k r freq 41.2k r ith2 20k mtop1, mtop2, mbot1, mbot2: rjk0651dpb l1: coilcraft ser1360-802kl l2: coilcraft ser1360-472kl c out1 : 16svp180mx c out2 : sanyo 6tpe470m d1, d2: dfls1100 d1 d2 ltc3890 r sense1 9m r sense2 10m l1 8h l2 4.7h mbot1 tg1 mtop1 v out1 12v 3a v in 12.5v to 60v 3890 ta04 intv cc 100k 100k c b1 0.47f r a2 18.7k sw1 v out2 5v 5a sw2 boost1 c b2 0.47f boost2 v in intv cc pgnd tg2 bg2 c out2 470f c int 4.7f c in 220f mbot2 c2 1nf high efficiency dual 12v/5v step-down converter
ltc3890 35 3890fb typical a pplica t ions mtop2 sense1 + sense1 ? v fb1 track/ss2 ith2 v fb2 sense2 ? sense2 + ith1 track/ss1 i lim phsmd clkout pllin/mode sgnd extv cc run1 run2 freq pgood2 bg1 c ith1a 100pf c ith1 680pf c ss2 0.01f c ss1 0.01f c ith2 470pf c1 1nf c out1 22f 2 ceramic r b1 487k r a1 16.9k c f1 33pf r ith1 46k r freq 60k r ith2 20k mtop1, mtop2, mbot1, mbot2: rjk0651dpb l1: sumida cdr7d43mn l2: coilcraft ser1360-472kl c out1 : kemet t525d476mo16e035 c out2 : sanyo 6tpe470m d1, d2: dfls1100 d1 d2 ltc3890 l1 22h l2 4.7h mbot1 tg1 mtop1 v out1 24v 1a v in 28v to 60v 3890 ta05 intv cc 100k pgood1 100k c b1 0.47f r a2 18.7k r b2 100k c2 1nf sw1 v out2 5v 5a sw2 boost1 c b2 0.47f boost2 v in intv cc pgnd tg2 bg2 c out2 470f c int 4.7f c in 220f mbot2 r sense1 25m r sense2 10m high efficiency dual 24v/5v step-down converter
ltc3890 36 3890fb typical a pplica t ions 12v sepic and 3.3v step-down converter mtop2 sense1 + sense1 ? v fb1 track/ss2 ith2 v fb2 sense2 ? sense2 + ith1 track/ss1 i lim phsmd clkout pllin/mode sgnd extv cc run1 run2 freq pgood2 pgood1 bg1 c ith1a 47pf c ith1 10nf c ss2 0.01f c ith2a 47pf c ss1 0.01f c ith2 4.7nf c1 1nf r a1 6.98k r b1 100k r ith1 12.1k 511 r b2 100k r freq 41.2k r ith2 7.15k m1, mbot1, mbot2: rjk0651dpb l1: wrth 7448709100 l2: wrth 7443320330 c out1 : sanyo 16tqc68m c out2 : sanyo 6tpe470m d1: dfls1100 d2: pds560 d1 ltc3890 r sense2 4m l2 3.3h m1 tg1 v in 5v to 35v 3890 ta06 intv cc intv cc v out1 v out1 c b1 0.1f r mode 100k r a2 31.6k sw1 v out2 3.3v 10a v out1 12v 2a sw2 boost1 c b2 0.1f boost2 v in intv cc pgnd tg2 bg2 c out2 470f c int 4.7f c in 100f r sns1 6m mbot2 c2 1nf 2k 2k 1k 0.1f ?? 10h 10h l1 6.8f 511 d2 6.8f 6.8f c out 68f
ltc3890 37 3890fb typical a pplica t ions high efficiency 12v at 25a dual-phase step-down converter mtop2 sense1 + sense1 ? v fb1 track/ss2 ith2 v fb2 sense2 ? sense2 + ith1 track/ss1 i lim phsmd clkout pllin/mode sgnd freq run1 run2 pgood2 bg1 c ith1a 100pf c ith1 4.7nf c ss1 0.1f c1 1nf c out1 150f r b1 499k r a1 35.7k 10pf r ith1 9.76k r freq 30.1k v in v out mtop1, mtop2, mbot1, mbot2: rjk0651dpb l1, l2: wrth 7443631000 c out1 , c out2 : sanyo 16svpc150m c in : sun elect. 63ce100bs d1, d2: dfls1100 d1 d2 ltc3890 l1 10h l2 10h mbot1 tg1 mtop1 v out 12v 25a v in 16v to 60v 3890 ta07 intv cc pgood1 100k c b1 0.1f c2 1nf sw1 sw2 boost1 c b2 0.1f boost2 v in intv cc pgnd tg2 bg2 c out2 150f c int 4.7f c in 100f mbot2 r sense1 3m r sense2 3m extv cc r run1 1000k r run2 57.6k
ltc3890 38 3890fb p ackage descrip t ion uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3890 39 3890fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 01/11 added mp-grade and h-grade. changes reflected throughout the data sheet. 1-38 b 04/12 clarified the electrical characteristics specifications. added typical application schematics. 3, 36, 37
ltc3890 40 3890fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0412 rev b ? printed in usa r ela t e d p ar t s typical a pplica t ion high efficiency dual 12v/3.3v step-down converter part number description comments ltc3891 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, tssop-20e, 3mm 4mm qfn-20 ltc3857/ltc3857-1/ ltc3858/ltc3858-1 low i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a/170a ltc3834/ltc3834-1/ ltc3835/LTC3835-1 low i q , single output synchronous step-down dc/dc controllers with 99% duty cycle pll fixed frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a/80a ltc3810 100v synchronous step-down dc/dc controller constant on-time valley current mode, 4v v in 100v, 0.8v v out 0.93v in , ssop-28 ltc3859a low i q , triple output buck/buck/boost synchronous dc/dc controller with improved burst mode operation outputs (5v) remain in regulation through cold crank, 2.5v v in 38v, v out(bucks) up to 24v, v out(boost) up to 60v mtop2 sense1 + sense1 ? v fb1 track/ss2 ith2 v fb2 sense2 ? sense2 + ith1 track/ss1 i lim phsmd clkout pllin/mode sgnd extv cc run1 run2 freq pgood2 pgood1 bg1 c ith1a 100pf c ith1 470pf c ss2 0.01f c ss1 0.01f c ith2 1000pf c ith2a 100pf c1 1nf c out1 180f r a1 6.98k r ith1 34.8k r b1 100k r b2 100k r freq 41.2k r ith2 34.8k mtop1, mtop2, mbot1, mbot2: rjk0651dpb l1: coilcraft ser1360-802kl l2: coilcraft ser1360-472kl c out1 : 16svp180mx c out2 : sanyo 6tpe470m d1, d2: dfls1100 d1 d2 ltc3890 r sense1 9m r sense2 10m l1 8h l2 4.7h mbot1 tg1 mtop1 v out1 12v 3a v in 12.5v to 60v 3890 ta08 intv cc 100k 100k c b1 0.47f r a2 31.6k sw1 v out2 3.3v 5a sw2 boost1 c b2 0.47f boost2 v in intv cc pgnd tg2 bg2 c out2 470f c int 4.7f c in 220f mbot2 c2 1nf v out1

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